Inefficiency Constraints in Computer Design

Question: Discuss about the Inefficiency Constraints in Computer Design. Answer: Introduction: CPU, which is also known as, Central Processing Unit has a major part known as processor. The name of the processor is Intel Core i3/i5/i7. The code name is Ivy Bridge. The Lithography is 22nm. The Processor number is i5-3427U. The processor base frequency is 1.80 GHz. The CPU stepping number is Family 6 Model A Stepping 9. The core speed is 2310.24 MHz with multiplier x35 and the Bus speed 66.01MHz. The cache size is 32Kbytes. CPU has many free caches which incorporates instruction as well as data cache. Data cache is organized synchronically of cache levels L1, L2 AND L3. L1D cache is used for storing data and the size is 32Kbytes. L1I is used for storing instruction and the size is 32Kbytes. L2 caches are not split and are usually used for larger processor. The data get shared in the core and the size of the cache is 256Kbytes. L3 caches are used for higher level caches and the size is 3Mbytes. The memory is Extended Data Output RAM with a size 1024Mbytes. Dynamic Random Access Memory, which store the data temporarily and it fetches the information very quickly with high speed. Dram frequency is 66.0MHz. The ratio of FSB to DRAM is 1:1. The time for delaying the CAS(CL) IS 3 clocks. The RAS to CAS delay timing is also 3clocks. The timer set for DRAM Idler is 0clocks (Begum et al., 2016). GPU is also known as Graphics Processing Unit. GPU specification is VMware SVGA 3D. The board manufacture is 0*15AD (0*0405) and the size is 1024Mbytes. SVGA is not good when used for heavy applications in 3D (Cohen Cohen, 2016). The manufacturer of main board is Intel Corporation. The mode number is 44OBX Desktop Reference Platform. The chipset is of Intel with model number i440BX/ZX. The Southbridge is of Intel with model number 82371(PIIX4). Basic Input Output System is of Phoenix Technologies LTD. The version is 6.0 and the manufacturer date is 07/02/2015. Reference List Begum, R., Hempstead, M., Srinivasa, G. P., Challen, G. (2016, November). Algorithms for CPU and DRAM DVFS under inefficiency constraints. InComputer Design (ICCD), 2016 IEEE 34th International Conference on(pp. 161-168). IEEE. Cohen, D. Cohen, D. (2016). The Ultimate Guide To VMWare and 3D Graphics. TeraSky. Retrieved 20 December 2016, from https://www.terasky.com/ultimate-guide-vmware-3d-graphics/